FPGA Design

Join to apply for the FPGA Design - Principal Engineer / Lead Engineer / Senior Engineer / Engineer role at ASTRI - Hong Kong Applied Science and Technology Research Institute 2 weeks ago Be among the first 25 applicants Join to apply for the FPGA Design - Principal Engineer / Lead Engineer / Senior Engineer / Engineer role at ASTRI - Hong Kong Applied Science and Technology Research Institute Hong Kong Applied Science and Technology Research Institute (ASTRI) was founded by the Government of the Hong Kong Special Administrative Region in 2000 with the mission of enhancing Hong Kong’s competitiveness through applied research.ASTRI’s core R&D competence in various areas is grouped under five Technology Divisions: Advanced Electronic Components and Systems; Artificial Intelligence and Trust Technologies; Communications Technologies; IoT Sensing and AI Technologies; and Intelligent Perception and Control Technologies.It is applied across six core areas which are Smart City, Financial Technologies, New Industrialisation and Intelligent Manufacturing, Digital Health, Application Specific Integrated Circuits and Metaverse.Over the years, ASTRI has nurtured a pool of research, I&T talents and received numerous international awards for its pioneering innovations as well as outstanding business and community contributions.As of 2023/24, ASTRI has transferred more than 1,500 technologies to the industry and has been granted over 1,100 patents in the Mainland, the US, and other countries.Job ResponsibilitiesTo support our constant endeavour to position Hong Kong as a world-class smart city and an international hub of innovation and technology, we are seeking qualified professionals to fill the following position(s):Participate and contribute to physical layer (PHY) FPGA solution development in multiple platforms in ASTRI’s 5G/6G R&D projects Engage in activities including the followings: Develop high performance wireless communications FPGA solutions for 5G/6G L1 Physical (PHY) layer Optimize and troubleshoot FPGA solutions in target platforms to fulfil high performance and real time deadline requirements Perform RTL coding, synthesis, Implementation, and speed & area optimization in FPGA Design testbench and conduct simulations & on-board debugging Co-work with hardware and software Engineer in development Troubleshoot and setup hardware platforms for development Build up know-hows on 5G/6G standardization Job RequirementsPhD holder or Master or Bachelor’s in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, Information Engineering, Telecommunications, or relevant disciplines Successfully completed the undergraduate/postgraduate program Fresh graduates may also be considered Knowledge of wireless communications standard, such as 5/6G, ORAN, WiFi, Bluetooth a plus Experience with Verilog RTL coding and testbench design Familiar with large FPGA development on Xilinx devices Experience with Xilinx’s build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure Experience with scripting languages: Python, tcl or equivalent, a plus Lives ASTRI values ApplicationThe appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical, insurance coverage and contribution to MPF. The incumbent will normally work a five-day week.For interested parties, please submit your application with detailed CV within two weeks of the post date. Applicants are encouraged to submit their applications as soon as possible. The review of applications will continue until the post is filled.The resume should not include any sensitive personal information such as ID card no. or passport number, photo, etc.Position offer is subject to the applicant’s experience and academic qualification. Only short-listed candidates will be notified. ASTRI reserves the right not to fill the position.ASTRI is an Equal Opportunities Employer. Personal data provided by job applicants will be used exclusively for recruitment only. For details, please refer to ASTRI Privacy Policy Statement. Seniority level Seniority level Mid-Senior level Employment type Employment type Full-time Job function Job function Engineering and Information Technology Industries IT Services and IT Consulting Referrals increase your chances of interviewing at ASTRI - Hong Kong Applied Science and Technology Research Institute by 2x Sign in to set job alerts for “Principal Design Engineer” roles. Shenzhen, Guangdong, China CN¥30,000.00-CN¥60,000.00 2 years ago Senior Optics Design Engineer, OPD Hardware Shenzhen, Guangdong, China CN¥50,000.00-CN¥80,000.00 1 year ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI. #J-18808-Ljbffr