Chief Engineer

ACCESS is a multi-disciplinary center for advancing IC design and design automation technologies to enable novel data-centric computing paradigms supporting a wide range of AI applications. The research agenda in ACCESS is organized into four research programs, addressing four key technical areas, including 1) Computing-in-Memory Architecture for Large-scale AI Models, 2) Hardware-Software Co-Design for Energy-Efficient and High-Performance Edge AI, 3) EDA (Electronic Design Automation) for Large-Scale AI Hardware, and 4) Cross-layer Optimization and Demonstration for Targeted Applications. Responsibilities The Chief Engineer / Chief Architect (ASIC Design) will be involved in the development of multiple research programs and projects in the Center and will co‑lead whole‑flow digital/analog/mixed‑signal ASIC designs from architecture to tape‑out for one or multiple research programs. He/she will assist the Director and Executive Director in overseeing all aspects of R&D management, collaboration projects with industry, outsourcing, and engineering supports for multiple research projects or research facilities. He/she should be hands‑on in design and implementation tasks, as well as leading junior research/engineer staff, in one or multiple research projects in the Center. The Chief Engineer / Chief Architect (ASIC Design) is required to station and work at the Hong Kong Science Park, with occasional business travels to the HKUST Clear Water Bay Campus and other collaborating universities of the Center when needed. Requirements Applicants should have a PhD degree preferably in electronics, electrical or computer engineering, computer science, or equivalent, and at least 8 years of post‑qualification experience in R&D or equivalent. In‑depth knowledge and experience in integrated circuit design, design automation or broadly microelectronics are essential. Specifically, R&D as well as hands‑on implementation experiences in the following area(s) with relevance to the design of AI accelerators are preferred (but not limited to): Hands‑on experience of the entire SoC/ASIC design flow with experiences in multiple digital/mixed‑signal IC tape‑outs. Solid experience with synthesis, floorplanning, CTS, P&R, timing closure, STA, DRC/LVS/LEC/CDC checks, power analysis, EM & IR analysis using industry standard tools & methodologies. Experience with SoC issues such as multiple voltages and clock domains, ESD strategies, low power design; experience in integrating IP from both internal and external vendors and specifying physical requirements. Familiar with hierarchical design approach, top‑down design, budgeting, timing, and physical convergence. Experience in advanced node process below 28 nm process and/or analog circuit custom layout is a plus. The ideal candidate should have strong R&D capability and superior interpersonal and organizational skills. He/She should be an excellent team‑player with a strong sense of responsibility, ability to multi‑task and work independently, and a good command of written and spoken English. Outstanding verbal, written and presentation skills are also required. Terms of Appointment Starting salary will be commensurate with qualifications and experience. Fringe benefits including annual leave, medical and dental benefits will be provided. ACCESS is an equal opportunity employer and welcomes applications from all qualified candidates. Application Procedure For applications/nominations, please apply with a full curriculum vitae indicating your current and expected salaries. Review of applications will begin shortly and continue until the positions are filled. Only shortlisted candidates will be notified. Information provided by applications will be used for recruitment and other employment‑related purposes. #J-18808-Ljbffr