Physical Design Engineer

5 days ago


hong kong, Hong Kong SAR China eTopus Technology (HK) Limited Full time

Job Descriptions Place and route, clock tree synthesis, extraction, timing closure in leading edge technology Low power design methodology with power domains/UPF/CPF Physical verification(DRC/LVS/ERC) IR drop and EM analysis Automate and improve design flow Qualifications Bachelor’s or Master’s degree in EE/CE/CS or related field 5+ years hands-on experience in full-chip/block level place and route, floorplanning, power planning, chip integration, ECO flows, timing closure, power and clock optimization, formal verification, IR/EM analysis and physical verification Knowledge of RTL-to-GDS flow, synthesis, static-timing-analysis, lower power design, DFT, IP hardening Scripting skills using TCL, Perl, python, or shell Tape-out experience in 22nm / 12nm process nodes or below The ability to work independently and on a team while interfacing with team members located in Hong Kong / China / US / Canada #J-18808-Ljbffr



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